Anodic Processing for Multilevel LSI

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Abstract
Anodic processing for multilevel LSI is attractive because planar structures can be made. For complete flexibility of design, it is advantageous that portions of the first level of interconnection metallization be isolated initially from silicon, and that the required contact to silicon be made using overpasses on a subsequent level. Anodic processes previously described required that there be a direct contact to silicon for each land to be defined. This restriction can be circumvented by depositing a thin conductive layer before deposition of the interconnection metallurgy and eventually converting it to an insulator. The requirements for a suitable underlay are given, and the choice of hafnium for this purpose is explained. The details of the anodic processing are described and discussed. Conversion of the underlay to an insulator requires both anodization until barrier layer growth ceases and oxidation at elevated temperature; 450°C in steam for 30 min yields excellent results. The leakage current between closely spaced conductors is decreased substantially by the use of this underlay process as compared to the previously descibed anodic processes.

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