ShiftQ

1 January 2001

proceedings article
Published by Association for Computing Machinery (ACM)

p. 158-167
https://doi.org/10.1145/502217.502243

Abstract

ShiftQs are hardware structures consisting of registers and switches which buffer and transport operands among function units within custom hardware loop accelerators. ShiftQs help minimize buffering and interconnect costs by customizing the hardware to the given schedule and by intelligent sharing of register and interconnect resources. This paper describes the ShiftQ schema and a method to automatically synthesize them from modulo-scheduled loops. We also evaluate the cost savings by comparing them against traditional storage and interconnect mechanisms.

Keywords

HARDWARE STRUCTURE
INTELLIGENT SHARING
TRANSPORT OPERANDS
SHIFTQ SCHEMA
CUSTOM HARDWARE LOOP ACCELERATOR
COST SAVING
TRADITIONAL STORAGE
MODULO-SCHEDULED LOOP
CUSTOM LOOP ACCELERATOR
SHIFTQS HELP
FUNCTION UNIT
FUNCTIONAL UNIT
PREEMPTION
SHARED MEMORY
RTOS
SOC

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