A statistical method for test sequence evaluation

1 June 1988

proceedings article
Published by Association for Computing Machinery (ACM)

p. 338-341
https://doi.org/10.1145/62882.62921

Abstract

A method for test sequence evaluation based on random sampling of detectable faults is presented. This method can be incorporated into most logic simulation codes which use the parallel machine method of fault detection.

Keywords

DETECTABLE FAULT
PARALLEL MACHINE METHOD
TEST SEQUENCE EVALUATION
RANDOM SAMPLING
LOGIC SIMULATION CODE
FAULT DETECTION
STATISTICAL METHOD
INTEGRATED CIRCUIT
SEQUENTIAL CIRCUITS
STATISTICAL MECHANICS
SYSTEM ANALYSIS

This publication has 1 reference indexed in Scilit:

On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets
IEEE Transactions on Electronic Computers, 1966