Control logic modelling scheme well suited to test problem

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Abstract
Each VLSI circuit includes some blocks used to convert data, to give the microprocessor commands, and some programmable logic array blocks. These blocks are called random logic blocks. To propagate the test data through these random logic blocks, combinatorial or synchronous sequential, explicit knowledge is required of the input/output combinations that can functionally be generated. The usual representations of the random logic are unsuitable for this because they have not been designed for this purpose. A new model has been developed to obtain this knowledge. It makes clearer all the possible input/output combinations, and it allows direct simulations and inferences through all kinds of random logic blocks.

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