Efficient CMOS counter circuits

13 October 1988

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 24 (21) , 1311-1313
https://doi.org/10.1049/el:19880891

Abstract

Several efficient counters are presented. A nine-transistor divide-by-two circuit is used as a basic building block. With transistor sizing, an input frequency of 400 MHz can be adopted by an asynchronous counter, while an eight-bit synchronous counter can achieve clock rates of more than 200 MHz in a 3μm CMOS process. The power consumption of the proposed precharged dynamic synchronous counter is reduced to almost half as much as normal.

Keywords

PRECHARGED DYNAMIC SYNCHRONOUS COUNTER
BASIC BUILDING BLOCK
POWER CONSUMPTION
CLOCK RATES
TRANSISTOR SIZING
INPUT FREQUENCY
CMOS PROCESS
ASYNCHRONOUS COUNTER
CMOS COUNTER CIRCUITS
DIVIDE-BY-TWO CIRCUIT

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