High resolution ADC using phase modulation-demodulation architecture
- 1 June 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Applied Superconductivity
- Vol. 9 (2) , 3016-3019
- https://doi.org/10.1109/77.783664
Abstract
We report successful demonstration of a fully operational integrated superconducting ADC system based on a phase modulation/demodulation architecture. It consists of a high-resolution ADC chip with a multiple-chann el race arbiter and integrated bit- pipelined decimation filter, an interface electronics block converting the ADC output to standard ECL form at sampling rates up to 200 MHz, and a computerized test station performing data acquisition, processing and display in real time. We have demonstrated a fully functional 14-bit ADC chip with 2-channel race arbiter and 16-bit decimation filter with 1:64 decimation ratio operating at 11.2 GS/s. By using additional decimation filtering of the ADC output at room temperature we demonstrated its dynamic programmability and resolution-bandwidth tradeoff. The measured ADC performance (in effective bits) was competitive with the best semiconductor high-resolution ADCs.Keywords
This publication has 2 references indexed in Scilit:
- High resolution ADC systemIEEE Transactions on Applied Superconductivity, 1997
- Superconducting high-resolution A/D converter based on phase modulation and multichannel timing arbitrationIEEE Transactions on Applied Superconductivity, 1995