CODYMOS frequency dividers achieve low power consumption and high frequency

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Abstract
Frequency dividers made with complementary dynamic m.o.s. (CODYMOS) circuits require only a small number of transistors and interconnections, a single input signal and operate with a minimum number of successive transitions. This leads to a drastic reduction in stray capacitance and current consumption, and to an increase in speed. A simplified analysis of these quantities is given for binary and ternary dividers. An experimental circuit, integrated with silicon-gate technology, operates from a 1.35 V battery, divides by 3 up to an input frequency in excess of 20 MHz and draws a current of 0.4 μA/MHz.

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