On the design of IEEE compliant floating point units

22 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 54-63
https://doi.org/10.1109/arith.1997.614879

Abstract

Engineering design methodology recommends designing a system as follows: start with an unambiguous specification, partition the system into blocks, specify the functionality of each block, design each block separately, and glue the blocks together. Verifying the correctness of an implementation then reduces to a local verification procedure. We apply this methodology for designing a provably correct, modular, IEEE-compliant floating point unit. First, we provide a mathematical, and hopefully unambiguous, definition of IEEE Standard 754 (1985) which specifies the functionality. The design consists of an adder, a multiplier and a rounding unit, each of which is further partitioned. Our floating point unit design deals with the detection of exceptions and trapped overflow and underflow exceptions as an integral part of the rounding unit. Our abstraction level avoids bit-level arguments while still enabling the addressing of crucial implementation issues such as delay and cost.

Keywords

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