A VLSI image pipeline processor

1 January 1984

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVII, 208-209
https://doi.org/10.1109/isscc.1984.1156719

Abstract

A 6.9mm×7mm chip with 115K transistors, produced in 1.75μm E/D NMOS technology, will be covered. Data flow architecture with a 10MHz clock rate enables a 3×3 convolution of a 512 × 512 gray image to be performed in 3 seconds by one chip or 1:1 seconds using three cascaded chips.

Keywords

VERY LARGE SCALE INTEGRATION
PIPELINE PROCESSING
TESTING
DIGITAL IMAGES
COMPUTER ARCHITECTURE
CONVOLUTION
PIXEL
INTEGRATED CIRCUIT SYNTHESIS
INTEGRATED CIRCUIT TECHNOLOGY
PARALLEL PROCESSING

This publication has 1 reference indexed in Scilit:

A preliminary architecture for a basic data-flow processor
Published by Association for Computing Machinery (ACM) ,1975