High speed switch scheduling for local area networks

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Abstract
Current technology trends make it possible to build communication networks that can support highperformance dktributed computing. This paper describes issues in the design of a prototype switch for a point-to-point network with link speeds of up to one gigabit per second. The switch deals in fixed-length ATM-style cells, w~lch it can process at a rate of 37 million cells per second. It provides high bandwidth and low latency for datagram traffic. In addition, it supports real-time traffic by providing bandwidth reservations with guaranteed latency bounds. The key to the switch’s operation is a technique called parallel iterative matching, which can quickly identify a set of con fllctfree cells for transmission in a time slot. Bandwidth reservations are accommodated in the switch by building a fixed schedule for transporting cells from reserved flows across the switch; parallel iterative matching can be used to fill unused slots with datagram traffic. Finally, we note that parallel iterative matching may not allocate bandwidth fairly among flows of datagram traffic. We describe a technique called statistical matching, which can be used. to ensure fairness at the switch and also to support applications with rapidly changing needs for guaranteed bandwidth.

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