An 8-k bit random-access memory chip using a one-device FET cell

• 1 January 1973
• conference paper
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• p. 64-65
• https://doi.org/10.1109/isscc.1973.1155147

Abstract

Keywords

• FETS
• DECODING
• REGISTERS
• LABORATORIES
• DRIVER CIRCUITS
• CHIP SCALE PACKAGING
• INVERTERS
• MINIMIZATION
• GEOMETRY
• PRODUCTIVITY