A VLSI-suitable Schottky-barrier CMOS process
- 1 February 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 32 (2) , 194-202
- https://doi.org/10.1109/t-ed.1985.21929
Abstract
Trenched Schottky-barrier (TSB) contact PMOS devices for use in latchup-free CMOS are examined in detail, and compared to Schottky-contact PMOS. Measurements and simulations show that the TSB structure has significant advantages in gain and current leakage over the Schottky-contact structure. CMOS using TSB PMOS may be made unconditionally free of latchup. The tradeoffs involving PMOS source-drain implant dose are made explicit and correlated to latchup measurements.Keywords
This publication has 0 references indexed in Scilit: