An efficient parallel algorithm for digital IIR filters
- 24 March 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1, 525-528
- https://doi.org/10.1109/icassp.1976.1170109
Abstract
A parallel algorithm is presented which speeds up the operation of arbitrary infinite impulse response (IIR) digital filters by an integer factor n. When n is a power of two or highly composite a special numerator factorization significantly reduces the number of multipliers required for large n. The resulting filter can operate at a sampling rate exceeding the inverse of a multiply time. Hence, such filters are not multiplier speed limited. The IIR algorithm is shown to share the desirable property of the FIR algorithm that when resampling is done at the output, part of the filter hardware can be eliminated. The IIR parallel algorithm implements a degenerate filter form. The implications of this on practical filter design are considered and a design example given. It is shown that implementations of these parallel filters can exhibit reduced sensitivity allowing a reduction in the multiplier constant length.Keywords
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