Bus connected neural network hardware system
- 9 June 1994
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 30 (12) , 979-980
- https://doi.org/10.1049/el:19940666
Abstract
The authors describe a hardware implementation of a neural network system consisting of bus connected binary neurons. The single binary neuron consists of an FPGA chip, a PLA chip, a 2 kbyte S-RAM chip, and several SSI chips. Eight binary neurons are fabricated on a single printed board. As a trial production run, five neuron boards were fabricated. Three neural network applications were installed on the developed system, and were confirmed to work well. All binary neurons in the system can calculate their states in parallel after receiving an ID number of a fired neuron within 300ns. Thus the binary neural network system leads to a solution ~600 times faster than a software simulator on a DEC5100.Keywords
This publication has 1 reference indexed in Scilit:
- Neural Network Parallel ComputingPublished by Springer Nature ,1992