Comparison of latch-up in p- and n-well CMOS circuits

Abstract
The latch-up hardness of p- and n-well CMOS concepts is compared for processes with and without epitaxial layer using electrical and laser-scanning measurements as well as theoretical calculations. It is shown that latch-up hardness does not primarily depend on the parasitic bipolar gain products, which are different for the two concepts, but rather on the shunt resistors in the well and in the substrate. This leads to equal latch-up hardness for n- and p-well concepts without epitaxy. With epitaxy latch-up hardness is strongly increased and is in the case of a p-well by a factor of 5 higher compared with the n-well concept. This is due to the enhanced diffusion of Boron from the p+-substrate in the epitaxial layer.

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