Delay optimization of carry-skip adders and block carry-lookahead adders
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The worst-case carry propagation delays in carry-skip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. The authors report a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under the proposed delay model, critical path delay is calculated taking into account not only the intrinsic gate delays but also the fanin and fanout contributions.<>Keywords
This publication has 17 references indexed in Scilit:
- A Way to Build Efficient Carry-Skip AddersIEEE Transactions on Computers, 1987
- Some optimal schemes for ALU implementation in VLSI technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Limitations on Carry Lookahead NetworksIEEE Transactions on Computers, 1984
- A note on finding convex hulls via maximal vectorsInformation Processing Letters, 1980
- A hybrid approach to discrete mathematical programmingMathematical Programming, 1978
- On the Average Number of Maxima in a Set of Vectors and ApplicationsJournal of the ACM, 1978
- Branch-and-Bound Strategies for Dynamic ProgrammingOperations Research, 1976
- Methods for the Solution of the Multidimensional 0/1 Knapsack ProblemOperations Research, 1967
- Capital Budgeting of Interrelated Projects: Survey and SynthesisManagement Science, 1966
- Discrete-Variable Extremum ProblemsOperations Research, 1957