A neural network design for circuit partitioning

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Vol. 9 (12) , 1265-1271
https://doi.org/10.1109/43.62771

Abstract

A neural network model is proposed for circuit bipartitioning. The massive parallelism of neural nets has been successfully exploited to balance the partitions of circuit and to reduce the external wiring between the partitions. The experimental results obtained by neural nets are found to be comparable with those achieved by the C.M. Fiduccia and R.M. Mattheyses (1982) algorithm. The proposed approach can be implemented in hardware to accelerate time-consuming partitioning procedures

Keywords

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