3-D SOI/CMOS

1 January 1984

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 792-795
https://doi.org/10.1109/iedm.1984.190846

Abstract

Three-dimensional (3-D) SOI/CMOS has been expected to be a novel structure which offers the possibilities of high packing density and high speed function. This paper summarizes some of the properties of 3-D SOI/CMOS such as fabricating processes, characteristics and practical structures.

Keywords

CRYSTALLIZATION
SILICON ON INSULATOR TECHNOLOGY
INSULATION
TEMPERATURE
HEATING
CMOS PROCESS
IMPURITIES
STRIPS
CMOS INTEGRATED CIRCUITS
HIGH SPEED INTEGRATED CIRCUITS