A polysilicon transistor technology for large capacity SRAMs

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 469-472
https://doi.org/10.1109/iedm.1990.237066

Abstract

A polysilicon PMOS cell technology is discussed. Bottom-gated polysilicon PMOS transistors are stacked over NMOS transistors, and a 17 mu m/sup 2/ cell size is realized with a 0.6 mu m design rule. In order to achieve high-performance polysilicon PMOS, both gate oxide and channel polysilicon thicknesses of the PMOS are reduced to 40 nm. A 0.4 mu m length gate-to-drain offset structure is adopted. Moreover, two novel approaches to O/sub 2/ plasma treatment prior to metal H/sub 2/-N/sub 2/ anneal and oxidation of channel polysilicon have been found to be effective for achieving excellent polysilicon PMOS characteristics. As a result, polysilicon PMOS which has a 25 fA off-current (V/sub d/=-5 V, V/sub g/=0 V) and a 0.1 nA on-current (V/sub d/=-5 V, V/sub g/=-2 V) has been realized.<>

Keywords

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