Effect of thermal annealing on thin film transistors processed by photoengraving

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Abstract
Thin film transistors (TFTs) are of current interest for addressing large-area flat panel displays. In most cases, in-vacuum mechanical masking and successive evaporations in a single pumpdown have been used to define the necessary patterns. While this has the advantage of minimizing contamination of the film interfaces, complex and expensive equipment is needed to fabricate high resolution patterns over large areas. We have, therefore, investigated the use of conventional vacuum deposition and photoengraving processes, similar to those used in silicon integrated circuit technology, and have successfully fabricated CdSe TFTs in which the gate and source-drain levels have been defined by photoengraving. Al and Cr metallizations and Al2O3 dielectric layers have been used. Well-saturated transistors with switching ratios of ∠104 and electron mobilities of ∠50 cm2 V−1 s−1 are achieved only after the fabricated structure is thermally annealed. Since some thermal annealing appears to be essential in all of the reported TFT processes, the physical significance of thermal annealing has been investigated. A model involving activated diffusion is presented and the effect of different annealing conditions on transistor characteristics discussed.

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