High-speed architectures for morphological image processing

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Abstract
This paper presents a dual architecture for the high-speed realization of basic morphological operations. Since morphological filtering can be described as a combination of erosion and dilation, two basic building blocks are required for the realization of any morphological filter. Architectures for the two basic units, namely the erosion unit and the dilation unit, are proposed and studied in terms of cycle time, hardware complexity, and cost. These basic units are similar in structure to the systolic array architecture used in the implementation of linear digital filters. Correspondingly, the proposed units are highly modular and are suitable for efficient VLSI implementation. These basic units allow the processing of either binary or gray-scale images. They are particularly suitable for applications in robotics, where speed, size and cost are of critical importance.

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