A 32Mb chain FeRAM with segment/stitch array architecture

22 December 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 1 (01936530) , 282-493
https://doi.org/10.1109/isscc.2003.1234302

Abstract

A 96mm/sup 2/, 32Mb chain FeRAM in 0.20/spl mu/m 3M CMOS and stacked capacitor technology is described. Cell efficiency of 65.6% is realized by compact memory cell structure and segment/stitch WL architecture. The word line power-on/off sequence protects the data from startup noise. A 3/spl mu/A standby current bias generator and compatible access mode SRAM are implemented for mobile applications.

Keywords

RANDOM ACCESS MEMORY
FERROELECTRIC FILMS
NONVOLATILE MEMORY
CAPACITORS
VOLTAGE
WIRING
CMOS TECHNOLOGY
CIRCUITS
DELAY
PROTECTION

This publication has 1 reference indexed in Scilit:

A 76-mm/sup 2/ 8-Mb chain ferroelectric memory
IEEE Journal of Solid-State Circuits, 2001