Vertical enhancement-mode InP MISFET's fabricated on n-type substrate

1 September 1986

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 7 (9) , 549-551
https://doi.org/10.1109/edl.1986.26468

Abstract

We report a new vertical structure InP enhancement-mode MISFET. These transistors are made on an Fe-doped semi-insulating InP epitaxial layer grown by organometallic vapor-phase epitaxy (OMVPE) on an n-type InP substrate. Thermally evaporated borosilicate is used as the gate insulator. Transconductances as high as 100 mS/mm have been achieved with a gate length of approximately 2.8µm. The novelty and potential advantages of the vertical structure are discussed.

Keywords

INDIUM PHOSPHIDE
SUBSTRATES
IMPLANTS
INSULATION
FETS
ETCHING
EPITAXIAL GROWTH
MISFETS
ELECTRON MOBILITY
THERMAL CONDUCTIVITY

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