Two-terminal transistor memory cell using breakdown

Publisher Website

1 January 1971

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 10-11
https://doi.org/10.1109/isscc.1971.1154948

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

h_FEdegradation due to reverse bias emitter-base junction stress
IEEE Transactions on Electron Devices, 1969
Degradation Phenomena of Planar Si Devices Due to Surface and Bulk Effects
Fourth Annual Symposium on the Physics of Failure in Electronics, 1967