On channel segmentation design for row-based FPGAs
- 1 January 1992
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The channel segmentation design problem for row-based field-programmable gate arrays (FPGAs) is to design a segmented channel to maximize the probability of successful routing. An algorithm which takes an arbitrary net distribution and an integer K (specifying the maximum number of segments allowed in routing a net) as inputs, and automatically generates a segmented channel which is most suitable for K-segment channel routing is presented. The algorithm was tested extensively over various net distributions. An algorithm for segmented channel routing based on reducing the problem to the maximum independent set problem for undirected graphs is also presented.Keywords
This publication has 4 references indexed in Scilit:
- An MPGA Compatible FPGA ArchitecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Segmented channel routingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Approximating maximum independent sets by excluding subgraphsBIT Numerical Mathematics, 1992
- An architecture for electrically configurable gate arraysIEEE Journal of Solid-State Circuits, 1989