A novel architecture design for VLSI implementation of an FIR decimation filter
- 23 March 2005
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 10, 1380-1383
- https://doi.org/10.1109/icassp.1985.1168287
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- A Use of Double Integration in Sigma Delta ModulationIEEE Transactions on Communications, 1985
- A Voiceband Codec with Digital FilteringIEEE Transactions on Communications, 1981
- Interpolation and decimation of digital signals—A tutorial reviewProceedings of the IEEE, 1981
- On multistage finite impulse response (FIR)filters with decimationIEEE Transactions on Acoustics, Speech, and Signal Processing, 1975