Accurate technique for CV Measurements on SOI structures excluding parasitic capacitance effects

1 September 1986

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 7 (9) , 537-539
https://doi.org/10.1109/EDL.1986.26464

Abstract

A simple technique is proposed to determine accurate CV curves free from the influence of parasitic capacitance which is inherent to silicon-on-insulator (SOI) structures. The method is based on capacitance measurements between the various terminals and their interpretation according to an appropriate equivalent circuit. Typical results obtained for a mesa-isolated SIMOX capacitor are given.

Keywords

CAPACITANCE MEASUREMENT
PARASITIC CAPACITANCE
SUBSTRATES
CAPACITORS
SEMICONDUCTOR FILMS
EQUIVALENT CIRCUITS
SILICON ON INSULATOR TECHNOLOGY
INTEGRATED CIRCUIT INTERCONNECTIONS
MICROELECTRONICS