Reliability evaluation of von neumann multiplexing based defect-tolerant majority circuits

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Abstract
The nanometer scale of device manufacturing in the semiconductor industry is characterized by two features (i) high defect rate at the substrate, and (ii) availability of large number of devices on chip. The high defect rate is due to manufacturing defects, ageing, transient faults and quantum physical effects, which need to be circumvented by designing reliable architectures in the nanotechnology era. The availability of higher device count, however, will allow designers to implement redundancy based defect-tolerance. Various structural redundancy based defect tolerance have been proposed in the past including multiplexing, triple modular redundancy, cascaded triple modular redundancy etc. Information redundancy based on coding techniques have been proposed as well. However, redundant parts of the design are also affected by defects, and therefore, redundancy level needs to be suitably chosen to obtain reliable architec- ture. Our past work has concentrated on various structural redundancy techniques, including von Neumann's NAND multiplexing, and we have shown how to use a probabilistic model checking tool to evaluate redundancy/reliability trade- off points for such designs. In this paper, we concentrate on a specific circuit, namely, majority circuit to evaluate its redundancy/reliability trade-off. This special attention to majority circuits is motivated by the recent advances in non-silicon technologies for nanoscale computing, such as Quantum Dot Cellular Automata, which use three input majority gates as their basic logic devices. Our results in this paper show that reliability of majority circuits when multiplexed using von-Neumann's technique admits lesser reliability at the same level of redundancy than in case of NAND gates. This is significant due to the growing importance of the majority gates in implementing various logic functions in emerging nanotechnologies.

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