Design SRAMs for burn-in

30 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 164-170
https://doi.org/10.1109/vtest.1993.313330

Abstract

SRAM designers and product engineers must balance the diverse aspects involved in developing and manufacturing quality ICs. This paper describes how cost and complexity design techniques to improve burn-in, noting implications for performance, power and density.

Keywords

RANDOM ACCESS MEMORY
COSTS
CIRCUIT TESTING
BUILT-IN SELF-TEST
AGING
CHIP SCALE PACKAGING
COMPRESSORS
CONDUCTORS
HEATING
OVENS

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