Time Redundant Fault-Location in Bit-Sliced ALU's
- 1 November 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-36 (11) , 1387-1389
- https://doi.org/10.1109/TC.1987.5009483
Abstract
A method of fault location in arithmetic and logic units (ALU's) is proposed. When the failures are confined to adjacent bit slices of the ALU's, the RESO (recomputing with shifted operands) based method can isolate the faulty bit slices by specifying a larger set of ``suspicious'' faulty bit slices, and, therefore, identify the definitely fault-free bit slices in ALU's. The method is applicable to both arithmetic and logic operations.Keywords
This publication has 5 references indexed in Scilit:
- Fault-Tolerant Computing—Concepts and ExamplesIEEE Transactions on Computers, 1984
- Concurrent Error Detection in ALU's by Recomputing with Shifted OperandsIEEE Transactions on Computers, 1982
- The STAR (Self-Testing And Repairing) Computer: An Investigation of the Theory and Practice of Fault-Tolerant Computer DesignIEEE Transactions on Computers, 1971
- Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System DesignIEEE Transactions on Computers, 1971
- Error Codes for Arithmetic OperationsIEEE Transactions on Electronic Computers, 1966