A fast offset-free sample-and-hold circuit
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 5.6/1-5.6/3
- https://doi.org/10.1109/cicc.1988.20806
Abstract
A sample-and-hold stage is described that uses a CMOS cascode inverter and a novel switching scheme. Since the output voltage need not slew back to the V/sub os/ voltage level, the new circuit does not need to have an excessively high slew rate. The experimental results show that a high-speed and small-chip-area sample-and-hold circuit can be obtained when small-geometry (1- mu m design rule) devices are available.Keywords
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