QCDOC: A 10-teraflops scale computer for lattice QCD

Preprint

1 November 2000

preprint
Published by arXiv in arXiv

https://doi.org/10.48550/arXiv.hep-lat/0011004

Abstract

The architecture of a new class of computers, optimized for lattice QCD calculations, is described. An individual node is based on a single integrated circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor communications and additional control and diagnostic circuitry. The machine's name, QCDOC, derives from ``QCD On a Chip''.

Keywords

INTEGRATED CIRCUIT
TERAFLOPS SCALE
SCALE COMPUTER
ARCHITECTURE
LATTICE QCD
DIAGNOSTIC
QCDOC

All Related Versions

Version 1, 2000-11-01, ArXiv
Published version: Nuclear Physics B - Proceedings Supplements, 94 (1-3), 825.

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