A Josephson latch
- 1 October 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (5) , 583-590
- https://doi.org/10.1109/jssc.1978.1051104
Abstract
A latch has been developed which is suitable for use in a high-speed Josephson latching-logic computer. Measurements on a test chip incorporating latch circuits have shown that the flip-flop is capable of changing states in ~120 ps and that races can be prevented by deriving timing information from the AC power waveform. Details of the design and experimental results are given.Keywords
This publication has 3 references indexed in Scilit:
- Josephson quantum interference computer devicesIEEE Transactions on Magnetics, 1977
- A subnanosecond Josephson tunneling memory cell with nondestructive readoutIEEE Journal of Solid-State Circuits, 1975
- Dynamic behavior of Josephson tunnel junctions in the subnanosecond rangeJournal of Applied Physics, 1973