Memory consistency and event ordering in scalable shared-memory multiprocessors
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- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A new model of memory consistency, called release consistency, that allows for more buffering and pipelining than previously proposed models is introduced. A framework for classifying shared accesses and reasoning about event ordering is developed. The release consistency model is shown to be equivalent to the sequential consistency model for parallel programs with sufficient synchronization. Possible performance gains from the less strict constraints of the release consistency model are explored. Finally, practical implementation issues are discussed, with the discussion concentrating on issues relevant to scalable architectures.<>Keywords
This publication has 6 references indexed in Scilit:
- The directory-based cache coherence protocol for the DASH multiprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Parallel implementation of OPS5 on the encore multiprocessor: Results and analysisInternational Journal of Parallel Programming, 1988
- Efficient and correct execution of parallel programs that share memoryACM Transactions on Programming Languages and Systems, 1988
- Correct memory operation of cache-based multiprocessorsPublished by Association for Computing Machinery (ACM) ,1987
- Memory access buffering in multiprocessorsACM SIGARCH Computer Architecture News, 1986
- How to Make a Multiprocessor Computer That Correctly Executes Multiprocess ProgramsIEEE Transactions on Computers, 1979