Performance analysis of multistage interconnection networks with shared-buffered switching elements for ATM switching
- 1 January 1992
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 124-131 vol.1
- https://doi.org/10.1109/infcom.1992.263537
Abstract
The performance evaluation of multistage self-routing interconnection networks for asynchronous transfer mode (ATM) switching is carried out by means of an analytical approach. The switching elements in the interconnection network are provided with a buffer shared among all the inlets and outlets of the element and no backpressure signals are exchanged between adjacent stages. Two analytical models are considered: the scalar model and the vectorial model. In the former case the addresses of the packets in the same buffer are assumed to be mutually independent, whereas in the latter case the model keeps memory of the addresses of the packets stored in the buffer across consecutive time slots. The vectorial model provides performance measures much more accurate than the scalar model.Keywords
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