Abstract
We present a novel approach that minimizes the power consumption of embedded core - based systems through hard - ware/software partitioning Our approach is based on the idea of mapping clusters of operations/instructions to a core that yields a high utilization rate of the involved resources (ALUs, multipli - ers, shifters, ) and thus minimizing power consumption Our ap - proach is comprehensive since it takes into consideration the power consumption of a whole embedded system comprising a micropro - cessor core, application specifi c (ASIC) core(s), cache cores and a memory core We report high reductions of power consumption between 35% and 94% at the cost of a relatively small additional hardware overhead of less than 16k cells while maintaining or even slightly increasing the performance compared to the initial design

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