Design of MOS networks in single-rail input logic for incompletely specified functions
- 1 March 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 7 (3) , 339-345
- https://doi.org/10.1109/43.3167
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- Automated Logic Design of Mos NetworksPublished by Springer Nature ,1985
- Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate NetworksIEEE Transactions on Computers, 1979
- Synthesis Algorithms for 2-level MOS NetworksIEEE Transactions on Computers, 1975
- Minimal Negative Gate NetworksIEEE Transactions on Computers, 1972
- Gate-Interconnection Minimization of Switching Networks Using Negative GatesIEEE Transactions on Computers, 1971
- Synthesis of Networks with a Minimum Number of Negative GatesIEEE Transactions on Computers, 1971