Error correction technique for multivalued MOS memory
- 18 July 1991
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 27 (15) , 1321-1323
- https://doi.org/10.1049/el:19910831
Abstract
An error correction technique is proposed to increase the noise margin of a multivalued MOS memory. The stored voltage information is first converted to a binary representation. The noise margin of the store voltage is then increased by storing and comparing the least significant bits of the binary representation.Keywords
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