A clock feedthrough reduction circuit for switched-current systems
- 1 January 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 28 (2) , 133-137
- https://doi.org/10.1109/4.192044
Abstract
No abstract availableThis publication has 8 references indexed in Scilit:
- Switched currents-a new technique for analog sampled-data signal processingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Current-feedthrough effects and cancellation techniques in switched-current circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Switched-current system cellsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Switched-current circuit design issuesIEEE Journal of Solid-State Circuits, 1991
- A new design methodology of second order switched-current filterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- A CMOS switched-current filter techniquePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- CMOS switched-current ladder filtersIEEE Journal of Solid-State Circuits, 1990
- Switch-induced error voltage on a switched capacitorIEEE Journal of Solid-State Circuits, 1984