A sub-100 picosecond bipolar ECL technology

1 January 1985

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iedm.1985.190884

Abstract

A fully Self-Aligned Polysilicon bipolar transistor with Trench structure (SAPT) has been developed for its application in high-performance ECL circuits. An ECL gate delay of 80 ps was obtained with a transistor designed with 2 micron lithography (1.5 um emitter). This new transistor structure with two levels of polysilicon and trench technique for isolation promises to become very attractive for giga-bit digital systems.

Keywords

CAPACITANCE
DRY ETCHING
SILICON
BIPOLAR TRANSISTORS
BORON
DELAY
BIPOLAR TRANSISTOR CIRCUITS
LITHOGRAPHY
DIGITAL SYSTEMS
PLASMA APPLICATIONS

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