The Impact of Layout on Stress-Enhanced Transistor Performance

1 January 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 19461569,p. 143-146
https://doi.org/10.1109/sispad.2005.201493

Abstract

This paper studies the sensitivity of stress-enhanced transistor performance to layout variations. Stress simulations and mobility models are calibrated and verified for test structures with SiGe source/drain as a stressor. The role of STI on the stress transfer is explored. The numerical results show that variations of 15% in drive currents and of 44% in hole mobility due to layout induced stress variations can occur in the cases studied. These deviations need to be taken into account in circuit design or to be compensated via layout modification.

Keywords

THERMAL STRESSES
COMPRESSIVE STRESS
SILICON GERMANIUM
GERMANIUM SILICON ALLOYS
LATTICES
TRANSISTORS
TESTING
MOSFETS
NUMERICAL SIMULATION
THERMAL EXPANSION

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