A MIMD rendering algorithm for distributed memory architectures
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We present a parallel rendering algorithm targeted to MIMD distributed-memory message-passing architectures. For maximum performance, the algorithm exploits both object-level and image level parallelism. The behavior of the algorithm is examined both analytically and experimentally. The results show that the choice of message size has a significant impact on performance. Scalability to large numbers of processors is found to be limited primarily by communication overheads. An experimental implementation for the Intel iPSC/860 confirms the analytical results and demonstrates increasing performance from 1 to 128 processors across a wide range of scene complexities.Keywords
This publication has 7 references indexed in Scilit:
- PixelFlow: high-speed rendering using image compositionPublished by Association for Computing Machinery (ACM) ,1992
- Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memoriesPublished by Association for Computing Machinery (ACM) ,1989
- Algorithms for Parallel Polygon RenderingPublished by Springer Nature ,1989
- A parallel processor architecture for graphics arithmetic operationsACM SIGGRAPH Computer Graphics, 1987
- Parallel processing approaches to hidden-surface removal in image spaceComputers & Graphics, 1985
- Simulation and expected performance analysis of multiple processor Z-buffer systemsACM SIGGRAPH Computer Graphics, 1980
- Special Feature A VLSI Geometry Processor For GraphicsComputer, 1980