Concordant memory-array design: an integrated statistical approach for high quality gigabit-DRAM design

1 January 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 163-166
https://doi.org/10.1109/icicdt.2005.1502621

Abstract

A concordant memory-array design incorporates device fluctuation statistically into the signal-to-noise ratio analysis in DRAM and represents the failed bits in a chip. The proposed technique gives us a quantitative evaluation of the memory array and assures the operation of the 1.4 V array of a 100 nm - 1 Gb DRAM. The calculated dependence of failed bit counts on the array voltage is in good agreement with the experimental results of a 512 Mbit DRAM chip.

Keywords

This publication has 4 references indexed in Scilit:

Concordant memory design using statistical integration for the billions-transistor era
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits
IEEE Journal of Solid-State Circuits, 2004
VLSI Memory Chip Design
Published by Springer Nature ,2001
A new analytical diode model including tunneling and avalanche breakdown
IEEE Transactions on Electron Devices, 1992