A high-speed monolithic InP MISFET integrated logic inverter

1 February 1981

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 28 (2) , 218-221
https://doi.org/10.1109/t-ed.1981.20315

Abstract

High dynamic range monolithic n-channel InP MISFET integrated inverter circuits with delay times of 350 ps have been fabricated on Fe-doped semi-insulating substrates using ion implantation for channel and contact regions and pyrolytic SiO2for the gate insulation. These circuits, consisting of two active elements, a 4-µm channel-length normally-off enhancement driver MISFET, and a 4-µm gate-length normally-on depletion load MISFET are designed for use in direct-coupled high-speed logic. In comparison to the dominant GaAs MESFET approach, the present circuit does not require level shifting and uses only a single power supply. WithV_{DD} = 12.4V these inverters exhibit logic swings of 11.2 V, noise margins of 4.5 and 3.2 V, and dc gain in the linear region of 3.1.

Keywords

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