6 ns cycle 256 kb cache memory and memory management unit
- 1 January 1993
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A cache and memory management unit (CAMMU) which accesses the various units in parallel and pipelines the results for 6-ns throughput with minimum latency is described. To fit two 5-ns 128-kb memories with 256 outputs each in a foundry ASIC (application-specific integrated circuit) process and still have area for the control logic and smaller memories, a four-transistor pseudo-static memory cell is used. Time-sharing data input circuits and sense amplifiers between the two cache memories further reduce area, and post-charge logic for word-line access and sensing gives 5-ns access time. This CAMMU uses postcharge logic in coordinated access of TLB, TAG, and cache.Keywords
This publication has 2 references indexed in Scilit:
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