The design of a charge-integrating modified floating-point ADC chip
- 1 June 2004
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 39 (6) , 895-905
- https://doi.org/10.1109/jssc.2004.827808
Abstract
One of the challenges posed by calorimeters in high-energy physics experiments is digitizing wide dynamic range charge signals at high rate to a specified precision. One response to this challenge is the development of the QIE (charge integrator and encoder) concept. A QIE chip divides the input signal into multiple ranges, with each range integrating a scaled fraction of the signal. The range integrators are offset so that for any given signal magnitude, only one range will be selected as valid. The selected range integrator output is digitized to form a mantissa, and a digital code associated with that range forms an exponent. The resulting modified floating-point output format gives approximately constant measurement precision over a wide dynamic range. Floating-point converter designs are usually tailored for a specific application. A general description of the QIE concept shows how parameters are chosen to suit the application. The design of a mixed-signal chip that has been produced for a specific experiment is presented.Keywords
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