Future BiCMOS technology for scaled supply voltage
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 429-432
- https://doi.org/10.1109/iedm.1989.74314
Abstract
A BiCMOS technology for future scaled supply voltage, V/sub x/, is described. Delay time reduction by around 100 ps is achieved by introducing a proposed base electrode surround emitter transistor (BEST). Two types of gates, CBiCMOS and BiNMOS, provide shorter gate delays and higher drivabilities than the CMOS gate even with V/sub s/, of 3.3 V. It is concluded that the innovations in the bipolar transistor structure BEST and in the CBiCMOS and BiNMOS gate circuit configuration are highly promising in comparison to CMOS ULSIs for future high-speed and high-density ULSIs operating at scaled supply voltages.<>Keywords
This publication has 1 reference indexed in Scilit:
- A theory of transistor cutoff frequency (fT) falloff at high current densitiesIRE Transactions on Electron Devices, 1962