Applying testability to an ASIC architectural core

Abstract

The device-level testing of an application-specific integrated circuit (ASIC) that is designed using VLSI cores and LSI peripheral cells is discussed. The Intel ASIC UCS51 microcontroller product family is described, and the UCS51 test methodology is compared to that of the Intel standard product 80C51. A solution that provides the ASIC customer with a flexible design environment without compromising device testing is accomplished by employing built-in test modes, which are designed into the microcontroller core and accessed through a minimal amount of device package pins.

Keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS
VERY LARGE SCALE INTEGRATION
CIRCUIT TESTING
LIFE TESTING
LOGIC TESTING
SEMICONDUCTOR DEVICE TESTING
LARGE SCALE INTEGRATION
PACKAGING
STANDARDS DEVELOPMENT
PINS

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