A ROM-less direct digital frequency synthesizer using segmented nonlinear digital-to-analog converter
- 13 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 165-168
- https://doi.org/10.1109/cicc.2001.929748
Abstract
A direct digital frequency synthesizer (DDFS) based on nonlinear digital-to-analog converter (DAC) is presented. A new technique is proposed to segment the nonlinear DAC such that high speed DDFS with low power consumption and small die area can be achieved. The DDFS has 12 bits of phase resolution and 11 bits of magnitude resolution. It was fabricated in a 0.25 μm CMOS process with an active area of 1.4 mm 2 . For a clock frequency of 300 MHz, the spurious free dynamic range (SFDR) is better than 50 dB with output frequencies up to 3/8 of the clock frequency Author(s) Jiandong Jiang Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA Lee, E.K.F.Keywords
This publication has 4 references indexed in Scilit:
- Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converterIEEE Journal of Solid-State Circuits, 1999
- A direct digital synthesizer with an on-chip D/A-converterIEEE Journal of Solid-State Circuits, 1998
- An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator TruncationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communicationsIEEE Journal of Solid-State Circuits, 1984