A 15nW standby power 64Kb CMOS RAM

1 January 1982

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXV, 260-261
https://doi.org/10.1109/isscc.1982.1156384

Abstract

A FULLY STATIC 8K x 8b CMOS RAM, with a six-transistor structure, an internally-clocked low-power circuit and a redundancy technique, together with double polysilicon CMOS processing will be covered. The RAM offers typically 15mW power dissipation at lMHz operation, 50nW for standby and 8011s typical access time. Recently, it has been realized that a resistive load NMOS cell with CMOS peripheral circuits can offer high density, high speed and low active power for static RAMs. However, even with an extremely high resistive load, standby power level is limited to around 25pW typically, for 16Kb integration¿, while sacrificing process margin. On the other hand, a six-transistor CMOS memory cell can provide standby current three orders of magnitude smaller, while maintaining much wider temperature and voltage range as well as noise margin. Obviously, a penalty for the performance is larger cell area.

Keywords

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Fully static 16Kb bulk CMOS RAM
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1980